
Hardware
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INSPECTA hardware manual Rev 1.86 page 11
2 Hardware
2.1 INSPECTA features
INSPECTA is a long PCI-board with connectors to plug on the camera-adpater. There are two versions: the one-
channel INSPECTA-S ot the four-channel INSPECTA-M.
Image memory is the Pcs main memory. A PCI bus-master-controller can burst-write data with up to 512 DWORDS
per burst into main memory with one PCI-clock per DWORD. ( >100Mbyte/sec maximum data-rate). The bus-master-
controller is 2-dimensional and can adress up to 4Gbyte without CPU intervention.
Recording of video-data is - independant for each channel - line oriented. Every HSYNC increments the approprate
line counter. This line counter addresses a static RAM, which contains the starting address of this line in frame-
memory. This RAM ( line-address-table ) can be written at any time by the driver software. This writing can also be
done partially, the starting line number can be arbitrary selected.
The line-address-table defines the order of video lines in frame-memory. De-interlacing ( combinig two fields to one
frame ) and reversing the frame ( bootom up ), for imagers who scan the last line first, can be accomplished by writing
the line-address-table accordingly.
With four channels, each channel can directly address up to 4096 lines in frame-memory. With one channel, 16380
lines can be addressed. The contents all addresses for one or four channels is called context. There are two contexts
available, one of them can be selected by software at any time. Thus 32768 lines can be managed in total without
rewriting the line-address-table.
INSPECTAM can also accomodate linescan cameras. It can generate an start of scan signal. A clock counter counts
pixelclocks up to 8192 with an additional prescaler of 16. The clock counter is programmable in steps of 32
clocks.The SOS signal is available at the analog or digital camera connector. The length of SOS is 16 pixel clocks.
The following blockdiagramm shows INSPECTA
2K * 32
FIFO
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